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・ Ente Priyappetta Muthuvinu
・ Ente Radio Trieste
・ Ente Sathrukkal
・ Enson Inoue
・ Ensonido
・ Ensoniq
・ Ensoniq ASR-10
・ Ensoniq AudioPCI
・ Ensoniq EPS
・ Ensoniq ES-5506 OTTO
・ Ensoniq ESQ-1
・ Ensoniq Fizmo
・ Ensoniq Mirage
・ Ensoniq MR61
・ Ensoniq PARIS
Ensoniq Signal Processor
・ Ensoniq Soundscape Elite
・ Ensoniq Soundscape OPUS
・ Ensoniq Soundscape S-2000
・ Ensoniq SoundscapeDB
・ Ensoniq SQ-80
・ Ensoniq TS 10
・ Ensoniq VFX
・ Ensor
・ Ensor-Keenan House
・ Ensoulment
・ Enspel
・ Enspijk
・ Enssa
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Ensoniq Signal Processor : ウィキペディア英語版
Ensoniq Signal Processor

The Ensoniq ESP was used in many of the company's musical instruments and on their Soundscape Elite PC ISA sound card. It was used to enhance the synthesizer's audio samples with digital effects, enhancing the realism of the overall sound.
The ESP chip was a custom digital signal processor (DSP) chip with over 75,000 transistors. It had an instruction set that was optimized for manipulating audio data, which has typical sample rates of between 10 kHz and 50 kHz. The ESP was capable of creating a wide range of digital effects including reverb, delay, echo, flanging, chorusing, harmonizing, equalization, and distortion, and was capable of generating multiple effects simultaneously.
The ESP was a VLSI device designed in a 1.0 micrometre double-metal CMOS process. The multiplicity and flexibility of the data paths in the ESP allowed many DSP operations to be accomplished in a minimum number of microinstructions steps. Its nominal instruction cycle was 250 ns, yielding program lengths from about 64 to 160 microinstructions at typical sample rates. Because the ESP chip was fully programmable, the range of effects was unlimited.
The major features of the ESP chip were:
*48 Pin DIP or 52 Pin PLCC
*Separate Address Generator ALU
*4 Programmable Serial I/O Channels (I²S or Sony Format)
*On-Chip Data and Microprogram Memory
*8-Bit Address/Data Multiplexed Host CPU Interface
*External Sample Rate Synchronization
*Multiplexed Addressing for Simple DRAM Interface
*Host Access to ESP DRAM
The architecture of the ESP chip was implemented by the following major components:
*ALU - 24-bit wide, capable of 16 different instructions
*Multiplier - 24x24 bit with dedicated 48 bit accumulator
*Separate Address Generator ALU
*Microinstruction Memory Array (160 x 45 bits)
*General Purpose Register Array (192 x 24 bits)
*23 Special Purpose Registers
*Three 24-bit wide data paths
*Serial Digital I/O (4 stereo channels, I2S or Sony)
*Host interface
==References==

*(Ensoniq Home Page ESP Datasheet ) by Ensoniq Corp., Semiconductors Information, 1998, retrieved December 25, 2005.

抄文引用元・出典: フリー百科事典『 ウィキペディア(Wikipedia)
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